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| LTC2404/LTC2408 4-/8-Channel 24-Bit Power No Latency TM ADCs FEATURES s s DESCRIPTIO s s s s s s s s s s Pin Compatible 4-/8-Channel 24-Bit ADCs Single Conversion Digital Filter Settling Time Simplifies Multiplexing 4ppm INL, No Missing Codes 4ppm Full-Scale Error 0.5ppm Offset 0.3ppm Noise Internal Oscillator--No External Components Required 110dB Min, 50Hz/60Hz Notch Filter Reference Input Voltage: 0.1V to VCC Live Zero--Extended Input Range Accommodates 12.5% Overrange and Underrange Single Supply 2.7V to 5.5V Operation Low Supply Current (200A) and Auto Shutdown The LTC(R)2404/LTC2408 are 4-/8-channel 2.7V to 5.5V micropower 24-bit A/D converters with an integrated oscillator, 4ppm INL and 0.3ppm RMS noise. They use delta-sigma technology and provide single cycle digital filter settling time (no latency delay) for multiplexed applications. The first conversion after the channel is changed is always valid. Through a single pin the LTC2404/ LTC2408 can be configured for better than 110dB rejection at 50Hz or 60Hz 2%, or can be driven by an external oscillator for a user defined rejection frequency in the range 1Hz to 120Hz. The internal oscillator requires no external frequency setting components. The converters accept any external reference voltage from 0.1V to VCC. With their extended input conversion range of -12.5% VREF to 112.5% VREF the LTC2404/LTC2408 smoothly resolve the offset and overrange problems of preceding sensors or signal conditioning circuits. The LTC2404/LTC2408 communicate through a flexible 4-wire digital interface which is compatible with SPI and MICROWIRETM protocols. , LTC and LT are registered trademarks of Linear Technology Corporation. No Latency is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. APPLICATIO S s s s s s s s s Weight Scales Direct Temperature Measurement Gas Analyzers Strain Gauge Transducers Instrumentation Data Acquisition Industrial Process Control 6-Digit DVMs TYPICAL APPLICATIO 7 MUXOUT 9 CH0 10 CH1 11 CH2 ANALOG INPUTS -0.12VREF TO 1.12VREF 12 CH3 4-/8-CHANNEL 13 CH4* MUX 14 CH5* 15 CH6* 17 CH7* 0.1V TO VCC 4 ADCIN 3 2, 8 VREF VCC CSADC CSMUX 24-BIT ADC SCK CLK DIN SDO LTC2404/LTC2408 GND 1, 5, 6, 16, 18, 22, 27, 28 *THESE PINS ARE NO CONNECTS ON THE LTC2404 FO 2404/08 TA01 2.7V TO 5.5V 1F SERIAL DATA LINK MICROWIRE AND SPI COMPATABLE LINEARITY ERROR (ppm) 23 20 19 25 21 24 MPU VCC 26 = INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION U Total Unadjusted Error vs Output Code 10 8 6 4 2 0 -2 -4 -6 -8 -10 0 8,338,608 OUTPUT CODE (DECIMAL) 16,777,215 2404/08 TA02 U U VDD = 5V VREF = 5V TA = 25C FO = LOW 1 LTC2404/LTC2408 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) to GND .......................- 0.3V to 7V Analog Input Voltage to GND ....... - 0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. - 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ - 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... - 0.3V to (VCC + 0.3V) PACKAGE/ORDER INFORMATION TOP VIEW GND VCC VREF ADCIN GND GND MUXOUT VCC CH0 1 2 3 4 5 6 7 8 9 28 GND 27 GND 26 FO 25 SCK 24 SDO 23 CSADC 22 GND 21 DIN 20 CSMUX 19 CLK 18 GND 17 NC 16 GND 15 NC ORDER PART NUMBER LTC2404CG LTC2404IG CH1 10 CH2 11 CH3 12 NC 13 NC 14 G PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 125C, JA = 130C/W Consult factory for Military grade parts. CONVERTER CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4) PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Full-Scale Error Full-Scale Error Drift Total Unadjusted Error Output Noise Normal Mode Rejection 60Hz 2% CONDITIONS 0.1V VREF VCC, (Note 5) VREF = 2.5V (Note 6) VREF = 5V (Note 6) 2.5V VREF VCC 2.5V VREF VCC 2.5V VREF VCC 2.5V VREF VCC VREF = 2.5V VREF = 5V VIN = 0V (Note 13) (Note 7) q q q q q q 2 U U W WW U W Operating Temperature Range LTC2404C/LTC2408C .............................. 0C to 70C LTC2404I/LTC2408I ........................... - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C TOP VIEW GND VCC VREF ADCIN GND GND MUXOUT VCC CH0 1 2 3 4 5 6 7 8 9 28 GND 27 GND 26 FO 25 SCK 24 SDO 23 CSADC 22 GND 21 DIN 20 CSMUX 19 CLK 18 GND 17 CH7 16 GND 15 CH6 ORDER PART NUMBER LTC2408CG LTC2408IG CH1 10 CH2 11 CH3 12 CH4 13 CH5 14 G PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 125C, JA = 130C/W U MIN 24 TYP 2 4 0.5 0.01 4 0.02 5 10 1.5 MAX 10 15 2 10 UNITS Bits ppm of VREF ppm of VREF ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF VRMS dB 110 130 LTC2404/LTC2408 CONVERTER CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4) PARAMETER Normal Mode Rejection 50Hz 2% Power Supply Rejection DC Power Supply Rejection 60Hz 2% Power Supply Rejection 50Hz 2% CONDITIONS (Note 8) VREF = 2.5V, VIN = 0V VREF = 2.5V, VIN = 0V, (Note 7) VREF = 2.5V, VIN = 0V, (Note 8) q A ALOG I PUT A D REFERE CE SYMBOL VIN VREF CS(IN) CS(REF) IIN(LEAK) IREF(LEAK) IIN(MUX) RON PARAMETER Input Voltage Range Reference Voltage Range Input Sampling Capacitance Reference Sampling Capacitance Input Leakage Current Reference Leakage Current On Channel Leakage Current MUX On-Resistance MUX RON vs Temperature RON vs VS (Note 15) IS(OFF) ID(OFF) tOPEN tON tOFF QIRR QINJ CS(OFF) CD(OFF) MUX Off Input Leakage MUX Off Output Leakage MUX Break-Before-Make Interval Enable Turn-On Time Enable Turn-Off Time MUX Off Isolation Charge Injection Input Off Capacitance (MUX) Output Off Capacitance (MUX) CS = VCC The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) CONDITIONS (Note 14) q q VREF = 2.5V, CS = VCC VS = 2.5V (Note 15) IOUT = 1mA, VCC = 2.7V IOUT = 1mA, VCC = 5V Channel Off, VS = 2.5V Channel Off, VD = 2.5V VS = 1.5V, RL = 3.4k, CL = 15pF VS = 1.5V, RL = 3.4k, CL = 15pF VIN = 2VP-P, RL = 1k, f = 100kHz RS = 0, CL = 1000pF, VS = 1V U U U U MIN 110 TYP 130 100 110 110 MAX UNITS dB dB dB dB U MIN - 0.125 * VREF 0.1 TYP MAX 1.125 * VREF VCC UNITS V V pF pF 10 15 q q q q q -10 - 12 1 1 250 120 0.5 20 10 12 20 300 250 nA nA nA %/C % q q 20 20 290 490 190 70 1 10 10 nA nA ns ns ns dB pC pF pF 3 LTC2404/LTC2408 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ VIN HMUX VIN LMUX PARAMETER High Level Input Voltage CS, FO Low Level Input Voltage CS, FO High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO Digital Input Current SCK Digital Input Capacitance CS, FO Digital Input Capacitance SCK High Level Output Voltage SDO Low Level Output Voltage SDO High Level Output Voltage SCK Low Level Output Voltage SCK High-Z Output Leakage SDO MUX High Level Input Voltage MUX Low Level Input Voltage V + = 3V V+ = 2.4V (Note 9) IO = - 800A IO = 1.6mA IO = - 800A (Note 10) IO = 1.6mA (Note 10) q q q q q q q The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) CONDITIONS 2.7V VCC 5.5V 2.7V VCC 3.3V 4.5V VCC 5.5V 2.7V VCC 5.5V 2.7V VCC 5.5V (Note 9) 2.7V VCC 3.3V (Note 9) 4.5V VCC 5.5V (Note 9) 2.7V VCC 5.5V (Note 9) 0V VIN VCC 0V VIN VCC (Note 9) q q q q q q POWER REQUIRE E TS SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Mode Sleep Mode Multiplexer Supply Current The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) CONDITIONS q ICC(MUX) 4 UW U U MIN 2.5 2.0 TYP MAX UNITS V V 0.8 0.6 2.5 2.0 0.8 0.6 -10 -10 10 10 VCC - 0.5V 0.4V VCC - 0.5V 0.4V -10 2 0.8 10 10 10 V V V V V V A A pF pF V V V V A V V MIN 2.7 TYP MAX 5.5 UNITS V A A A CS = 0V (Note 12) CS = VCC (Note 12) All Logic Inputs Tied Together VIN = 0V or 5V q q q 200 20 15 300 30 40 LTC2404/LTC2408 TI I G CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time FO = 0V FO = VCC External Oscillator (Note 11) Internal Oscillator (Note 10) External Oscillator (Notes 10, 11) (Note 10) (Note 9) (Note 9) (Note 9) Internal Oscillator (Notes 10, 12) External Oscillator (Notes 10, 11) (Note 9) q q q q q q q q SYMBOL fEOSC tHEO tLEO tCONV fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t6 Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7 to 5.5V unless otherwise specified, source input is 0. Note 4: Internal Conversion Clock source with the FO pin tied to GND or to VCC or to external conversion clock source with fEOSC = 153600Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz 2% (external oscillator). Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz 2% (external oscillator). Note 9: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in kHz. UW CONDITIONS q q q q q q MIN 2.56 0.5 0.5 TYP MAX 307.2 390 390 UNITS kHz s s ms ms ms kHz kHz 130.66 133.33 136 156.80 160 163.20 20480/fEOSC (in kHz) 19.2 fEOSC/8 45 250 250 1.64 1.67 1.70 256/fEOSC (in kHz) 32/fESCK (in kHz) 0 0 0 50 200 15 50 50 150 150 150 55 2000 Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 32-Bit Data Output Time External SCK 32-Bit Data Output Time CS to SDO Low Z CS to SDO High Z CS to SCK CS to SCK SCK to SDO Valid SDO Hold After SCK SCK Set-Up Before CS SCK Hold After CS % kHz ns ns ms ms ms ns ns ns ns ns ns ns ns (Note 10) (Note 9) (Note 5) q q q q q q Note 10: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance CLOAD = 20pF. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. FO = 0V or FO = VCC. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: For reference voltage values VREF > 2.5V the extended input of - 0.125 * VREF to 1.125 * VREF is limited by the absolute maximum rating of the Analog Input Voltage pin (Pin 3). For 2.5V < VREF 0.267V + 0.89 * VCC the input voltage range is - 0.3V to 1.125 * VREF. For 0.267V + 0.89 * VCC < VREF VCC the input voltage range is - 0.3V to VCC + 0.3V. Note 15: VS is the voltage applied to a channel input. VD is the voltage applied to the MUX output. 5 LTC2404/LTC2408 TYPICAL PERFOR A CE CHARACTERISTICS Total Unadjusted Error (3V Supply) 10 VCC = 3V VREF = 3V 10 5 ERROR (ppm) ERROR (ppm) 0 TA = -55C, -45C, 25C, 90C -5 0 ERROR (ppm) -10 0 0.5 1.0 1.5 2.0 INPUT VOLTAGE (V) 2.5 3.0 Positive Extended Input Range Total Unadjusted Error (3V Supply) 10 VCC = 3V VREF = 3V 5 ERROR (ppm) ERROR (ppm) 2 0 -2 -4 -6 -8 TA = -55C, -45C, 25C, 90C 0 TA = 90C -5 TA = - 45C TA = 25C ERROR (ppm) TA = - 55C -10 3.0 3.1 3.2 INPUT VOLTAGE (V) 3.3 24048 G04 Negative Extended Input Range Total Unadjusted Error (5V Supply) 10 VCC = 5V VREF = 5V 10 TA = 90C 5 RMS NOISE (ppm OF VREF) 5 ERROR (ppm) TA = 25C 0 TA = - 45C -5 TA = - 55C ERROR (ppm) -10 0 - 0.05 - 0.10 - 0.15 - 0.20 - 0.25 - 0.30 INPUT VOLTAGE (V) 24048 G07 6 UW 24048 G01 INL (3V Supply) VCC = 3V VREF = 3V 10 Negative Extended Input Range Total Unadjusted Error (3V Supply) VCC = 3V VREF = 3V TA = 90C 5 TA = -55C, -45C, 25C, 90C 5 TA = 25C 0 TA = - 45C -5 TA = - 55C -5 -10 0 0.5 1.0 1.5 2.0 INPUT VOLTAGE (V) 2.5 3.0 -10 0 - 0.05 - 0.10 - 0.15 - 0.20 - 0.25 - 0.30 INPUT VOLTAGE (V) 24048 G03 24048 G02 Total Unadjusted Error (5V Supply) 10 VCC = 5V 8 VREF = 5V 6 4 10 INL (5V Supply) VCC = 5V VREF = 5V 5 0 TA = -55C, -45C, 25C, 90C -5 -10 -10 0 1 3 2 INPUT VOLTAGE (V) 4 5 24048 G05 0 1 3 2 INPUT VOLTAGE (V) 4 5 24048 G06 Positive Extended Input Range Total Unadjusted Error (5V Supply) 20 VCC = 5V VREF = 5V Offset Error vs Reference Voltage VCC = 5V TA = 25C 15 TA = - 55C 0 TA = 90C -5 TA = - 45C TA = 25C 10 5 -10 5.0 5.1 5.2 INPUT VOLTAGE (V) 5.3 24048 G08 0 0 1 3 4 2 REFERENCE VOLTAGE (V) 5 24048 G10 LTC2404/LTC2408 TYPICAL PERFOR A CE CHARACTERISTICS RMS Noise vs Reference Voltage 20 VCC = 5V TA = 25C RMS NOISE (ppm OF VREF) OFFSET ERROR (ppm) 15 10 RMS NOISE (ppm) 5 0 0 1 3 4 2 REFERENCE VOLTAGE (V) Noise Histogram 1500 VCC = 5V VREF = 5V VIN = 0V RMS NOISE (ppm) 1.00 NUMBER OF READINGS 1000 OFFSET ERROR (ppm) 500 0 -1.0 - 0.5 0 0.5 1.0 OUTPUT CODE (ppm) Full-Scale Error vs Temperature 5.0 VCC = 5V VREF = 5V VIN = 5V FULL-SCALE ERROR (ppm) 10.0 FULL-SCALE ERROR (ppm) 2.5 7.5 FULL-SCALE ERROR (ppm) 0 - 2.5 - 5.0 - 50 -25 0 25 50 75 100 125 TEMPERATURE (C) 24048 G16 UW 24048 G10 24048 G13 Offset Error vs VCC 5.0 VREF = 2.5V TA = 25C 2.5 5.0 RMS Noise vs VCC VREF = 2.5V TA = 25C 0 2.5 - 2.5 5 - 5.0 2.7 3.2 3.7 4.2 VCC 4.7 5.2 24048 G11 0 2.7 3.2 3.7 4.2 VCC 4.7 5.2 24048 G12 RMS Noise vs CODE OUT 5.0 VCC = 5V VREF = 5V VIN = - 0.3V TO 5.3V TA = 25C Offset Error vs Temperature VCC = 5V VREF = 5V VIN = 0V 0.75 2.5 0.50 0 0.25 - 2.5 1.5 0 0 7FFFFF CODE OUT (HEX) FFFFFF 24048 G14 - 5.0 - 50 -25 0 25 50 75 100 125 TEMPERATURE (C) 24048 G15 Full-Scale Error vs Reference Voltage 6 VCC = 5V VIN = VREF 5 4 3 2 1 0 Full-Scale Error vs VCC 5.0 2.5 VREF = 2.5V VIN = 2.5V TA = 25C 3.2 3.7 4.2 VCC 4.7 5.2 24048 G18 0 1 3 4 2 REFERENCE VOLTAGE (V) 5 24048 G17 0 2.7 7 LTC2404/LTC2408 TYPICAL PERFOR A CE CHARACTERISTICS Conversion Current vs Temperature 230 220 VCC = 5.5V 30 25 SUPPLY CURRENT (A) SUPPLY CURRENT (A) 210 200 190 180 170 160 150 -50 -25 0 75 50 25 TEMPERATURE (C) 100 125 VCC= 2.7V VCC = 4.1V 15 10 5 0 -50 -25 VCC = 2.7V REJECTION (dB) PSRR vs Frequency at VCC -10 -30 REJECTION (dB) VCC = 4.1V VIN = 0V TA = 25C F0 = 0 REJECTION (dB) REJECTION (dB) -50 -70 -90 -110 -130 0 50 100 150 200 FREQUENCY AT VCC (Hz) 250 24048 G22 Rejection vs Frequency at VIN -60 -70 -80 REJECTION (dB) REJECTION (dB) -90 -100 -110 -120 -130 REJECTION (dB) -140 -120 15100 -12 -8 -4 0 4 8 12 INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%) 24048 G25 8 UW 24048 G19 Sleep Current vs Temperature 0 -20 VCC = 5.5V PSRR vs Frequency at VCC VCC = 4.1V VIN = 0V TA = 25C FO = 0 20 -40 -60 -80 15,360Hz 153,600Hz -100 -120 50 25 75 0 TEMPERATURE (C) 100 125 1 100 10k 1M FREQUENCY AT VCC (Hz) 24048 G21 24048 G20 PSRR vs Frequency at VCC 0 -20 -40 -60 -80 0 VCC = 4.1V VIN = 0V TA = 25C FO = 0 -20 -40 -60 -80 Rejection vs Frequency at VIN VCC = 5V VREF = 5V VIN = 2.5V FO = 0 -100 -120 15200 15250 15300 15350 15400 15450 15500 FREQUENCY AT VCC (Hz) 24048 G23 -100 -120 1 50 100 150 200 FREQUENCY AT VIN (Hz) 250 24048 G24 Rejection vs Frequency at VIN 0 -20 -40 -60 -80 VCC = 5V VREF = 5V VIN = 2.5V FO = 0 Rejection vs Frequency at VIN 0 -20 -40 -60 -80 -100 -100 SAMPLE RATE = 15.36kHz 2% 15200 15300 15400 FREQUENCY AT VIN (Hz) 15500 24048 G26 -120 -140 0 fS/2 INPUT FREQUENCY 24048 F23 fS LTC2404/LTC2408 TYPICAL PERFOR A CE CHARACTERISTICS INL vs Maximum Output Rate 24 22 20 INL (BITS) RESOLUTION (BITS)* 18 16 TA = 25C 14 TA = 90C 12 10 8 0 5 10 15 20 25 30 35 40 45 50 55 60 MAXIMUM OUTPUT RATE (Hz) 24048 G27 PIN FUNCTIONS GND (Pins 1, 5, 6, 16, 18, 22, 27, 28): Ground. Should be connected directly to a ground plane through a minimum length trace or it should be the single-point-ground in a single point grounding system. VCC (Pins 2, 8): Positive Supply Voltage. 2.7V VCC 5.5V. Bypass to GND with a 10F tantalum capacitor in parallel with 0.1F ceramic capacitor as close to the part as possible. VREF (Pin 3): Reference Input. The reference voltage range is 0.1V to VCC. ADCIN (Pin 4): Analog Input. The input voltage range is - 0.125 * VREF to 1.125 * VREF. For VREF > 2.5V the input voltage range may be limited by the pin absolute maximum rating of - 0.3V to VCC + 0.3V. MUXOUT (Pin 7): MUX Output. This pin is the output of the multiplexer. Tie to ADCIN for normal operation. CH0 (Pin 9): Analog Multiplexer Input. CH1 (Pin 10): Analog Multiplexer Input. CH2 (Pin 11): Analog Multiplexer Input. CH3 (Pin 12): Analog Multiplexer Input. CH4 (Pin 13): Analog Multiplexer Input. No connect on the LTC2404. CH5 (Pin 14): Analog Multiplexer Input. No connect on the LTC2404. CH6 (Pin 15): Analog Multiplexer Input. No connect on the LTC2404. CH7 (Pin 17): Analog Multiplexer Input. No connect on the LTC2404. CLK (Pin 19): Shift Clock for Data In. This clock synchronizes the serial data transfer into the MUX. For normal operation, drive this pin in parallel with SCK. CSMUX (Pin 20): MUX Chip Select Input. A logic high on this input allows the MUX to receive a channel address. A logic low enables the selected MUX channel and connects it to the MUXOUT pin for A/D conversion. For normal operation, drive this pin in parallel with CSADC. DIN (Pin 21): Digital Data Input. The multiplexer address is shifted into this input on the last four rising CLK edges before CSMUX goes low. CSADC (Pin 23): ADC Chip Select Input. A low on this pin enables the SDO digital output and following each conversion, the ADC automatically enters the Sleep mode and remains in this low power state as long as CSADC is high. A high on this pin also disables the SDO digital output. A low-to-high transition on CSADC during the Data Output UW Resolution vs Maximum Output Rate 24 22 20 18 16 VCC = VREF = 3V 14 12 10 8 0 *RESOLUTION = LOG(VREF/RMS NOISE) LOG (2) FO = EXTERNAL (20480 x MAXIMUM OUTPUT RATE) TA = 25C TA = 90C VCC = VREF = 5V VCC = 5V VREF = 5V F0 = EXTERNAL (20480 x MAXIMUM OUTPUT RATE) 5 10 15 20 25 30 35 40 45 50 55 60 MAXIMUM OUTPUT RATE (Hz) 24048 G28 U U U 9 LTC2404/LTC2408 PIN FUNCTIONS state aborts the data transfer and starts a new conversion. For normal operation, drive this pin in parallel with CSMUX. SDO (Pin 24): Three-State Digital Output. During the data output period this pin is used for serial data output. When the chip select CSADC is high (CSADC = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin can be used as a conversion status output. The conversion status can be observed by pulling CSADC low. SCK (Pin 25): Shift Clock for Data Out. This clock synchronizes the serial data transfer of the ADC data output. Data is shifted out of SDO on the falling edge of SCK. For normal operation, drive this pin in parallel with CLK. FO (Pin 26): Digital input which controls the ADC's notch frequencies and conversion time. When the FO pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter first null is located at 50Hz. When the FO pin is connected to GND (FO = OV), the converter uses its internal oscillator and the digital filter first null is located at 60Hz. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its clock and the digital filter first null is located at a frequency fEOSC/2560. The resulting output word rate is fEOSC /20480. FU CTIO AL BLOCK DIAGRA VCC GND CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 8-CHANNEL MUX ADC SERIAL INTERFACE DECIMATING FIR VREF DAC TEST CIRCUITS SDO 3.4k CLOAD = 20pF SDO Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z 24048 TC01 10 W U U U U U INTERNAL OSCILLATOR AUTOCALIBRATION AND CONTROL FO (INT/EXT) SDO SCK CSADC CSMUX CHANNEL SELECT 24048 BD DIN CLK VCC 3.4k CLOAD = 20pF Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z 24048 TC02 LTC2404/LTC2408 APPLICATIONS INFORMATION Converter Operation Cycle The LTC2404/LTC2408 are low power, 4-/8-channel deltasigma analog-to-digital converters with easy-to-use 4-wire interfaces. Their operation is simple and made up of four states. The converter operation begins with the conversion, followed by a low power sleep state and concluded with the data output (see Figure 1). Channel selection may be performed while the device is in the sleep state or at the conclusion of the data output state. The interface consists of serial data output (SDO), serial clock (CLK/SCK), chip select (CSADC/CSMUX) and data input (DIN). By tying SCK to CLK and CSADC to CSMUX, the interface requires only four wires. Initially, the LTC2404 or LTC2408 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in the sleep state, power consumption is reduced by an order of magnitude. The part remains in the sleep state as long as CSADC is logic HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Channel selection for the next conversion cycle is performed while the device is in the sleep state or at the end of the data output state. A specific channel is selected by applying a 4-bit serial word to the DIN pin on the rising edge of CLK while CSMUX is HIGH, see Figure 3 and Table 3. The channel is selected based on the last four bits clocked into the DIN pin before CSMUX goes low. If DIN is all 0's, the previous channel remains selected. In the example, Figure 3, the MUX channel is selected during the sleep state, just before the data output state begins. Once the channel selection is complete, the device remains in the sleep state as long as CSADC remains HIGH. Once CSADC is pulled low, the device begins outputting the conversion result. There is no latency in the conversion result. Since there is no latency, the first conversion following a change in input channel is valid and corresponds to that channel. The data output corresponds to the conversion just performed. This result is shifted out on the serial data output pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising CONVERT U W U U CHANNEL SELECT (SLEEP) SLEEP 1 CSADC AND SCK 0 DATA OUTPUT (CHANNEL SELECT) 24048 F01 Figure 1. LTC2408 State Transition Diagram edge of SCK, see Figure 3. The data output state is concluded once 32 bits are read out of the ADC or when CSADC is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. Through timing control of the CSADC and SCK pins, the LTC2404/LTC2408 offer two modes of operation: internal or external SCK. These modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Conversion Clock A major advantage delta-sigma converters offer over conventional type converters is an on-chip digital filter (commonly known as Sinc or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50 or 60Hz plus their harmonics. In order to reject these frequencies in excess of 110dB, a highly accurate conversion clock is required. The LTC2404/LTC2408 incorporate an on-chip highly accurate oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2404/ LTC2408 reject line frequencies (50 or 60Hz 2%) a minimum of 110dB. 11 LTC2404/LTC2408 APPLICATIONS INFORMATION Ease of Use The LTC2404/LTC2408 data output has no latency, filter settling or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing an analog input voltage is easy. The LTC2404/LTC2408 perform offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. Power-Up Sequence The LTC2404/LTC2408 automatically enter an internal reset state when the power supply voltage VCC drops below approximately 2.2V. When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with duration of approximately 0.5ms. The POR signal clears all internal registers within the ADC and initiates a conversion. At power-up, the multiplexer channel is disabled and should be programmed once the device enters the sleep state. The results of the first conversion following a POR are not valid since a multiplexer channel was disabled. Reference Voltage Range The LTC2404/LTC2408 can accept a reference voltage from 0V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter's effective resolution. On the other hand, a reduced reference voltage will improve the overall converter INL performance. The recommended range for the LTC2404/LTC2408 voltage reference is 100mV to VCC. Input Voltage Range The converter is able to accommodate system level offset and gain errors as well as system level overrange situations due to its extended input range, see Figure 2. VCC + 0.3V 9/8VREF VREF ABSOLUTE MAXIMUM INPUT RANGE 12 U W U U 1/2VREF NORMAL INPUT RANGE EXTENDED INPUT RANGE 0 -1/8VREF -0.3V 24048 F02 Figure 2. LTC2404/LTC2408 Input Range The LTC2404/LTC2408 converts input signals within the extended input range of - 0.125 * VREF to 1.125 * VREF. For large values of VREF this range is limited to a voltage range of - 0.3V to (VCC + 0.3V). Beyond this range the input ESD protection devices begin to turn on and the errors due to the input leakage current increase rapidly. Input signals applied to VIN may extend below ground by - 300mV and above VCC by 300mV. In order to limit any fault current, a resistor of up to 5k may be added in series with any channel input pin (CH0 to CH7) without affecting the performance of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between this series resistance and the channel input pin as low as possible; therefore, the resistor should be located as close as practical to the channel input pin. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Analog Input/Reference Current section. In addition, a series resistor will introduce a temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. Output Data Format The LTC2404/LTC2408 serial output data stream is 32 bits long. The first 4 bits represent status information indicating the sign, input range and conversion state. The next 24 bits are the conversion result, MSB first. The remaining 4 bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. LTC2404/LTC2408 APPLICATIONS INFORMATION Bit 31 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CSADC pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 30 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 29 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW. The sign bit changes state during the zero code. Bit 28 (forth output bit) is the extended input range (EXR) indicator. If the input is within the normal input range 0 VIN VREF, this bit is LOW. If the input is outside the normal input range, VIN > VREF or VIN < 0, this bit is HIGH. The function of these bits is summarized in Table 1. Table 1. LTC2404/LTC2408 Status Bits Input Range VIN > VREF 0 < VIN VREF VIN = 0+/0 - VIN < 0 Bit 31 EOC 0 0 0 0 Bit 30 DMY 0 0 0 0 Bit 29 SIG 1 1 1/0 0 Bit 28 EXR 1 0 0 1 Bit 27 (fifth output bit) is the most significant bit (MSB). Bits 27-4 are the 24-bit conversion result MSB first. Bit 4 is the least significant bit (LSB). CSMUX/CSADC SDO Hi-Z EOC BIT 31 BIT 30 SCK/CLK DIN EN D2 D1 D0 Figure 3. Typical Data Input/Output Timing U W U U Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may be included in averaging or discarded without loss of resolution. Data is shifted out of the SDO pin under control of the serial clock (SCK), see Figure 3. Whenever CSADC is HIGH, SDO remains high impedance and any SCK clock pulses are ignored by the internal data out shift register. In order to shift the conversion result out of the device, CSADC must first be driven LOW. EOC is seen at the SDO pin of the device once CSADC is pulled LOW. EOC changes in real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 31 (EOC) can be captured on the first rising edge of SCK. Bit 30 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 31st SCK and may be latched on the rising edge of the 32nd SCK pulse. On the falling edge of the 32nd SCK pulse, SDO goes HIGH indicating a new conversion cycle has been initiated. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the VIN pin is maintained within the - 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any input value from - 0.125 * VREF to 1.125 * VREF. For input voltages greater than 1.125 * VREF, the conversion result is clamped to the value corresponding to 1.125 * VREF. For input voltages below - 0.125 * VREF, the conversion result is clamped to the value corresponding to - 0.125 * VREF. tCONV "0" SIG EXT MSB LSB Hi-Z BIT 0 DON'T CARE 24048 F03 13 LTC2404/LTC2408 APPLICATIONS INFORMATION Channel Selection Typically, CSADC and CSMUX are tied together or CSADC is inverted and drives CSMUX. SCK and CLK are tied together and driven with a common clock signal. During channel selection, CSMUX is HIGH. Data is shifted into the DIN pin on the rising edge of CLK, see Figure 3. Table 3 shows the bit combinations for channel selection. In order to enable the multiplexer output, CSMUX must be pulled LOW. The multiplexer should be programmed after the previous conversion is complete. In order to guarantee the conversion is complete, the multiplexer addressing should be delayed a minimum tCONV (approximately 133ms for a 60Hz notch) after the data out is read. While the multiplexer is being programmed, the ADC is in a low power sleep state. Once the MUX addressing is complete, the data from the preceding conversion can be read. A new conversion cycle is initiated following the data read cycle with the analog input tied to the newly selected channel. Table 3. Logic Table for Channel Selection CHANNEL STATUS All Off CH0 CH1 CH2 CH3 CH4* CH5* CH6* CH7* *Not used for the LTC2404. EN 0 1 1 1 1 1 1 1 1 D2 X 0 0 0 0 1 1 1 1 D1 X 0 0 1 1 0 0 1 1 D0 X 0 1 0 1 0 1 0 1 Table 2. LTC2404/LTC2408 Output Data Format Input Voltage VIN > 9/8 * VREF 9/8 * VREF VREF + 1LSB VREF 3/4VREF + 1LSB 3/4VREF 1/2VREF + 1LSB 1/2VREF 1/4VREF + 1LSB 1/4VREF 0+/0 - -1LSB -1/8 * VREF VIN < -1/8 * VREF Bit 31 EOC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 30 DMY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 29 SIG 1 1 1 1 1 1 1 1 1 1 1/0** 0 0 0 Bit 28 EXR 1 1 1 0 0 0 0 0 0 0 0 1 1 1 Bit 27 MSB 0 0 0 1 1 1 1 0 0 0 0 1 1 1 Bit 26 0 0 0 1 1 0 0 1 1 0 0 1 1 1 Bit 25 0 0 0 1 0 1 0 1 0 1 0 1 1 1 Bit 24 1 1 0 1 0 1 0 1 0 1 0 1 0 0 Bit 23 1 1 0 1 0 1 0 1 0 1 0 1 0 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... Bit 4 LSB 1 1 0 1 0 1 0 1 0 1 0 1 0 0 Bit 3-0 SUB LSBs* X X X X X X X X X X X X X X *The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. **The sign bit changes state during the 0 code. 14 U W U U Frequency Rejection Selection (FO Pin Connection) The LTC2404/LTC2408 internal oscillator provides better than 110dB normal mode rejection at the line frequency and all its harmonics for 50Hz 2% or 60Hz 2%. For 60Hz rejection, FO (Pin 26) should be connected to GND (Pin 1) while for 50Hz rejection the FO pin should be connected to VCC (Pin 2). LTC2404/LTC2408 APPLICATIONS INFORMATION The selection of 50Hz or 60Hz rejection can also be made by driving FO to an appropriate logic level. A selection change during the sleep or data output states will not disturb the converter operation. If the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. When a fundamental rejection frequency different from 50Hz or 60Hz is required or when the converter must be synchronized with an outside source, the LTC2404/ LTC2408 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency fEOSC of the external signal must be at least 2560Hz (1Hz notch frequency) to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods tHEO and tLEO are observed. While operating with an external conversion clock of a frequency fEOSC, the LTC2404/LTC2408 provide better than 110dB normal mode rejection in a frequency range fEOSC/2560 4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from fEOSC/2560 is shown in Figure 4. Whenever an external clock is not present at the F O pin the converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode. The Table 4. LTC2404/LTC2408 State Duration State CONVERT Operating Mode Internal Oscillator External Oscillator FO = LOW (60Hz Rejection) FO = HIGH (50Hz Rejection) FO = External Oscillator with Frequency fEOSC kHz (fEOSC/2560 Rejection) FO = LOW/HIGH (Internal Oscillator) FO = External Oscillator with Frequency fEOSC kHz External Serial Clock with Frequency fSCK kHz MAXIMUM OUTPUT WORD RATE Duration 133ms 160ms 20480/fEOSC (In Seconds) -60 -70 -80 REJECTION (dB) -90 -100 -110 -120 -130 -140 -12 -8 -4 0 4 8 12 INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%) 24048 F04 SLEEP DATA OUTPUT Internal Serial Clock U W U U Figure 4. LTC2404/LTC2408 Normal Mode Rejection When Using an External Oscillator of Frequency fEOSC LTC2404/LTC2408 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. If the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. If the change occurs during the data output state and the converter is in the Internal SCK mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. Table 4 summarizes the duration of each state as a function of FO. As Long As CS = HIGH Until CS = 0 and SCK As Long As CS = LOW But Not Longer Than 1.67ms (32 SCK cycles) As Long As CS = LOW But Not Longer Than 256/fEOSCms (32 SCK cycles) As Long As CS = LOW But Not Longer Than 32/fSCKms (32 SCK cycles) 1 OWR = in Hz tCONVERT + tDATAOUTPUT 15 LTC2404/LTC2408 APPLICATIONS INFORMATION Using an External Clock for Faster Conversion Times The conversion time of the LTC2404/LTC2408 is determined by the conditions on the FO pin. If FO is connected to GND for 60Hz rejection, the conversion time is 133s. If FO is connected to VCC, the conversion time is 160s. For an externally supplied frequency of fEOSC(kHz), the conversion time is: tCONV = 20480/fEOSC (kHz) The resulting frequency rejection is: Notch Frequency = 8/tCONV The maximum output word rate is: The DC specifications are guaranteed for fEOSC up to a maximum of 307.2kHz, resulting in a maximum output word rate of approximately 15Hz. However, for faster rates at reduced performance, frequencies up to 1.22MHz can be used on the FO pin. Figures 5 and 6 show the INL and Resolution vs Output Rate. SERIAL INTERFACE The LTC2404/LTC2408 transmit the conversion results, program the channel selection, and receive the start of conversion command through a synchronous 4-wire interface (SCK = CLK, CSADC = CSMUX). During the conversion and sleep states, this interface can be used to assess the converter status. While in the sleep state this interface may be used to program an input channel. During the data output state it is used to read the conversion result. ADC Serial Clock Input/Output (SCK) The serial clock signal present on SCK (Pin 25) is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2404/LTC2408 creates its own serial clock by dividing the internal conversion clock by 8. In the External SCK mode of operation, the SCK pin is used as input. The internal or external SCK mode is selected on power-up and then reselected every time a HIGH-to-LOW transition is detected at the CSADC pin. If SCK is HIGH or floating at power-up or during this transition, the converter enters the internal SCK mode. If SCK is LOW at power-up or during this transition, the converter enters the external SCK mode. Multiplexer Serial Input Clock (CLK) Generally, this pin is externally tied to SCK for 4-wire operation. On the rising edge of CLK (Pin 19) with CSMUX held HIGH, data is serially shifted into the multiplexer. If CSMUX is LOW the CLK input will be disabled and the channel selection unchanged. Serial Data Output (SDO) The serial data output pin, SDO (Pin 24), drives the serial data during the data output state. In addition, the SDO pin OWR = 1 in Hz tCONVERT + tDATAOUTPUT 24 22 20 VCC = 5V VREF = 5V F0 = EXTERNAL (20480 x MAXIMUM OUTPUT RATE) INL (BITS) 18 16 TA = 25C 14 TA = 90C 12 10 8 0 5 10 15 20 25 30 35 40 45 50 55 60 MAXIMUM OUTPUT RATE (Hz) 24048 G27 Figure 5. INL vs Maximum Output Rate 24 22 FO = EXTERNAL (20480 x MAXIMUM OUTPUT RATE) TA = 25C TA = 90C VCC = VREF = 5V VCC = VREF = 3V 14 12 10 8 0 *RESOLUTION = LOG(VREF/RMS NOISE) LOG (2) RESOLUTION (BITS)* 20 18 16 5 10 15 20 25 30 35 40 45 50 55 60 MAXIMUM OUTPUT RATE (Hz) 24048 G28 Figure 6. Resolution vs Maximum Output Rate 16 U W U U LTC2404/LTC2408 APPLICATIONS INFORMATION is used as an end of conversion indicator during the conversion and sleep states. When CSADC (Pin 23) is HIGH, the SDO driver is switched to a high impedance state. This allows sharing the serial interface with other devices. If CSADC is LOW during the convert or sleep state, SDO will output EOC. If CSADC is LOW during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes LOW. The device remains in the sleep state until the first rising edge of SCK occurs while CSADC = 0. ADC Chip Select Input (CSADC) The active LOW chip select, CSADC (Pin 23), is used to test the conversion status and to enable the data output transfer as described in the previous sections. In addition, the CSADC signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The LTC2404/LTC2408 will abort any serial data transfer in progress and start a new conversion cycle anytime a LOW-to-HIGH transition is detected at the CSADC pin after the converter has entered the data output state (i.e., after the first rising edge of SCK occurs with CSADC = 0). Multiplexer Chip Select (CSMUX) For 4-wire operation, this pin is tied directly to CSADC or the output of an inverter tied to CSADC. CSMUX (Pin 20) is driven HIGH during selection of a multiplexer channel. On the falling edge of CSMUX, the selected channel is enabled and drives MUXOUT. Data Input (DIN) The data input to the multiplexer, DIN (Pin 21), is used to program the multiplexer. The input channel is selected by serially shifting a 4-bit input word into the DIN pin under the control of the multiplexer clock, CLK. Data is shifted into the multiplexer on the rising edge of CLK. Table 3 Table 5. LTC2404/LTC2408 Interface Timing Modes Configuration External SCK Internal SCK SCK Source External Internal Conversion Cycle Control CS and SCK CS Data Output Control CS and SCK CS Connection and Waveforms Figures 7, 8, 9 Figures 10, 11 U W U U shows the logic table for channel selection. In order to select or change a previously programmed channel, an enable bit (DIN = 1) must proceed the 3-bit channel select serial data. The user may set DIN = 0 to continually convert on the previously selected channel. SERIAL INTERFACE TIMING MODES The LTC2404/LTC2408's 4-wire interface is SPI and MICROWIRE compatible. This interface offers two modes of operation. These include an internal or external serial clock. The following sections describe both of these serial interface timing modes in detail. For both cases the converter can use the internal oscillator (FO = LOW or FO = HIGH) or an external oscillator connected to the FO pin. Refer to Table 5 for a summary. External Serial Clock (SPI/MICROWIRE Compatible) This timing mode uses an external serial clock (SCK) to shift out the conversion result, see Figure 7. This same external clock signal drives the CLK pin in order to program the multiplexer. A single CS signal drives both the multiplexer CSMUX and converter CSADC inputs. This common signal is used to monitor and control the state of the conversion as well as enable the channel selection. The serial clock mode is selected on the falling edge of CSADC. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CSADC falling edge. The serial data output pin (SDO) is Hi-Z as long as CSADC is HIGH. At any time during the conversion cycle, CSADC may be pulled LOW in order to monitor the state of the converter. While CSADC is LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Independent of CSADC, the device automatically enters the low power sleep state once the conversion is complete. 17 LTC2404/LTC2408 APPLICATIONS INFORMATION 2.7V TO 5.5V VCC 0.1V TO VCC -0.12VREF TO 1.12VREF FO VCC CSADC/ CSMUX SCK/CLK TEST EOC SDO Hi-Z Hi-Z TEST EOC BIT31 BIT30 BIT29 BIT28 BIT27 BIT26 SIG EXR MSB BIT4 LSB BIT0 SUB LSB Hi-Z TEST EOC DIN DON'T CARE EN D2 D1 D0 Figure 7. External Serial Clock Timing Diagram While the device is in the sleep state, prior to entering the data output state, the user may program the multiplexer. As shown in Figure 7, the multiplexer channel is selected by serial shifting a 4-bit word into the DIN pin on the rising edge of CLK (CLK is tied to SCK). The first bit is an enable bit that must be HIGH in order to program a channel. The next three bits determine which channel is selected, see Table 3. On the falling edge of CSMUX, the new channel is selected and will be valid for the first conversion performed following the data output state. Clock signals applied to the CLK pin while CSMUX is LOW (during the data output state) will have no effect on the channel selection. Furthermore, if DIN is held LOW or CLK is held LOW during the sleep state, the channel selection is unchanged. When the device is in the sleep state (EOC = 0), its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen while CSADC is LOW. Data is shifted out the SDO pin on each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK. On the 32nd falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) indicating a conversion is in progress. 18 U W U U = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2404/LTC2408 VREF CH0 TO CH7 MUXOUT ADCIN GND CSMUX CSADC SCK CLK DIN SDO SCK CS DON'T CARE 24048 F07 At the conclusion of the data cycle, CSADC may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CSADC may be driven HIGH setting SDO to Hi-Z. As described above, CSADC may be pulled LOW at any time in order to monitor the conversion status. For each of these operations, CSMUX may be tied to CSADC without affecting the selected channel. At the conclusion of the data output cycle, the converter enters a user transparent calibration cycle prior to actually performing a conversion on the selected input channel. This enables a 66ms (for 60Hz notch frequency) look ahead time for the multiplexer input. Following the data output cycle, the multiplexer input channel may be selected any time in this 66ms window by pulling CSADC HIGH and serial shifting data into the DIN pin, see Figure 8. While the device is performing the internal calibration, it is sensitive to ground current disturbances. Error currents flowing in the ground pin may lead to offset errors. If the SCK pin is toggling during the calibration, these ground disturbances will occur. The solution is to either drive the multiplexer clock input (CLK) separately from the ADC clock input (SCK), or program the multiplexer in the first 1ms following the data output cycle. The remaining 65ms may be used to allow the input signal to settle. LTC2404/LTC2408 APPLICATIONS INFORMATION CSADC/ CSMUX SCK/CLK TEST EOC SDO Hi-Z TEST EOC BIT31 BIT30 BIT29 BIT28 BIT27 BIT26 SIG EXR MSB BIT4 LSB BIT0 SUB LSB DIN DON'T CARE CONVERTER STATE CONV SLEEP Figure 8. Use of Look Ahead to Program Multiplexer After Data Output 2.7V TO 5.5V VCC 0.1V TO VCC -0.12VREF TO 1.12VREF FO VCC CSADC/ CSMUX SCK/CLK TEST EOC SDO Hi-Z Hi-Z TEST EOC BIT31 BIT30 BIT29 BIT28 BIT27 BIT26 SIG EXR MSB BIT9 BIT8 LSB DIN DON'T CARE EN D2 D1 D0 Figure 9. External Serial Clock with Reduced Data Output Length Timing Diagram Typically, CSADC remains LOW during the data output state. However, the data output state may be aborted by pulling CSADC HIGH anytime between the first rising edge and the 32nd falling edge of SCK, see Figure 9. On the rising edge of CSADC, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. U W U U EN D2 D1 D0 DON'T CARE DATA OUTPUT INTERNAL CALIBRATION 66ms LOOK AHEAD CONVERSION ON SELECTED CHANNEL 66ms CONVERT 24048 F08 133ms CONVERSION CYCLE (OUTPUT RATE = 7.5Hz) = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2404/LTC2408 VREF CH0 TO CH7 MUXOUT ADCIN GND CSMUX CSADC SCK CLK DIN SDO SCK CS DON'T CARE 24048 F09 Internal Serial Clock This timing mode uses an internal serial clock to shift out the conversion result and program the multiplexer, see Figure 10. A CS signal directly drives the CSADC input, while the inverse of CS drives the CSMUX input. The CS signal is used to monitor and control the state of the conversion cycles as well as enable the channel selection. The multiplexer is programmed during the data output 19 LTC2404/LTC2408 APPLICATIONS INFORMATION 2.7V TO 5.5V VCC 0.1V TO VCC -0.12VREF TO 1.12VREF FO VCC CSMUX tEOCtest CSADC SCKCLK TEST EOC SDO Hi-Z Hi-Z TEST EOC BIT31 BIT30 BIT29 BIT28 BIT27 BIT26 SIG EXR MSB BIT4 BIT3 BIT2 BIT1 BIT0 TEST EOC Hi-Z DIN DON'T CARE Figure 10. Internal Serial Clock Timing Diagram state. The internal serial clock (SCK) generated by the ADC is applied to the multiplexer clock input (CLK). In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled HIGH prior to the falling edge of CSADC. The device will not enter the internal serial clock mode if SCK is driven LOW on the falling edge of CSADC. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CSADC; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven. The serial data output pin (SDO) is Hi-Z as long as CSADC is HIGH. At any time during the conversion cycle, CSADC may be pulled LOW in order to monitor the state of the converter. Once CSADC is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. When testing EOC, if the conversion is complete (EOC = 0), the device will exit the sleep state and enter the data output 20 U W U U = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION CS 10k LTC2404/LTC2408 VREF CH0 TO CH7 MUXOUT ADCIN GND CSMUX CSADC SCK CLK DIN SDO SUB SUB SUB SUB LSB LSB LSB LSB LSB EN D2 D1 D0 DON'T CARE 24048 F10 state if CSADC remains LOW. In order to prevent the device from exiting the low power sleep state, CSADC must be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time tEOCtest after the falling edge of CSADC (if EOC = 0) or tEOCtest after EOC goes LOW (if CSADC is LOW during the falling edge of EOC). The value of tEOCtest is 23s if the device is using its internal oscillator (F0 = logic LOW or HIGH). If FO is driven by an external oscillator of frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CSADC is pulled HIGH before time tEOCtest, the device remains in the sleep state. The conversion result is held in the internal static shift register. If CSADC remains LOW longer than tEOCtest, the first rising edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data output cycle begins on this first rising edge of SCK and concludes after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output LTC2404/LTC2408 APPLICATIONS INFORMATION to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 32nd rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH, and a new conversion starts. While operating in the internal serial clock mode, the SCK output of the ADC may be used as the multiplexer clock (CLK). DIN is latched into the multiplexer on the rising edge of CLK. As shown in Figure 10, the multiplexer channel is selected by serial shifting a 4-bit word into the DIN pin on the rising edge of CLK. The first bit is an enable bit which must be HIGH in order to program a channel. The next three bits determine which channel is selected, see Table 3. On the rising edge of CSADC (falling edge of CSMUX), the new channel is selected and will be valid for the next conversion. If DIN is held LOW during the data output state, the previous channel selection remains valid. 2.7V TO 5.5V VCC 0.1V TO VCC -0.12VREF TO 1.12VREF FO CSMUX tEOCtest CSADC SCKCLK TEST EOC SDO Hi-Z Hi-Z TEST EOC BIT31 BIT30 BIT29 BIT28 BIT27 BIT26 SIG EXR MSB Hi-Z BIT12 BIT11 BIT10 BIT9 BIT8 TEST EOC DIN DON'T CARE Figure 11. Internal Serial Clock with Reduced Data Output Length Timing Diagram U W U U Typically, CSADC remains LOW during the data output state. However, the data output state may be aborted by pulling CSADC HIGH anytime between the first and 32nd rising edge of SCK, see Figure 11. On the rising edge of CSADC, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. If CSADC is pulled HIGH while the converter is driving SCK LOW, the internal pull-up is not available to restore SCK to a logic HIGH state. This will cause the device to exit the internal serial clock mode on the next falling edge of CSADC. This can be avoided by adding an external 10k pull-up resistor to the SCK pin or by never pulling CSADC HIGH when SCK is LOW. Whenever SCK is LOW, the LTC2404/LTC2408's internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven if the device is in the internal SCK timing VCC = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION CS 10k LTC2404/LTC2408 VREF CH0 TO CH7 MUXOUT ADCIN GND CSMUX CSADC SCK CLK DIN SDO EN D2 D1 D0 DON'T CARE 24048 F11 21 LTC2404/LTC2408 APPLICATIONS INFORMATION mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the LTC2404/LTC2408's internal pull-up remains disabled. Hence, SCK remains LOW. On the next falling edge of CSADC, the device is switched to the external SCK timing mode. By adding an external 10k pullup resistor to SCK, this pin goes HIGH once the external driver goes Hi-Z. On the next CSADC falling edge, the device will remain in the internal SCK timing mode. A similar situation may occur during the sleep state when CSADC is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go LOW. Once CSADC goes HIGH (within the time period defined above as tEOCtest), the internal pull-up is activated. For a heavy capacitive load on the SCK pin, the internal pull-up may not be adequate to return SCK to a HIGH level before CSADC goes LOW again. This is not a concern under normal conditions where CSADC remains LOW after detecting EOC = 0. This situation is easily avoided by adding an external 10k pullup resistor to the SCK pin. DIGITAL SIGNAL LEVELS The LTC2404/LTC2408's digital interface is easy to use. Its digital inputs (FO, CSADC, CSMUX, CLK, DIN and SCK in External SCK mode of operation) accept standard TTL/ CMOS logic levels and can tolerate edge rates as slow as 100s. However, some considerations are required to take advantage of exceptional accuracy and low supply current. The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are not generally active during the conversion state. In order to preserve the accuracy of the LTC2404/LTC2408, it is very important to minimize the ground path impedance which may appear in series with the input and/or reference signal and to reduce the current which may flow through this path. Pin 6 (GND) should be connected to a low resistance ground plane through a minimum length trace. The use of multiple via holes is recommended to further reduce the connection resistance. The LTC2404/ LTC2408's power supply current flowing through the 0.01 resistance of the common ground pin will develop a 2.5V offset signal. For a reference voltage VREF = 2.5V, this represents a 1ppm offset error. In an alternative configuration, Pin 6 (GND) of the converter can be the single-point-ground in a single point grounding system. The input signal ground, the reference signal ground, the digital drivers ground (usually the digital ground) and the power supply ground (the analog ground) should be connected in a star configuration with the common point located as close to Pin 6 as possible. The power supply current during the conversion state should be kept to a minimum. This is achieved by restricting the number of digital signal transitions occurring during this period. While a digital input signal is in the 0.5V to (VCC - 0.5V) range, the CMOS input receiver draws additional current from the power supply. It should be noted that, when any one of the digital input signals (FO, CSADC, CSMUX, DIN, CLK and SCK in External SCK mode of operation) is within this range, the LTC2404/LTC2408 power supply current may increase even if the signal in question is at a valid logic level. For micropower operation and in order to minimize the potential errors due to additional ground pin current, it is recommended to drive all digital input signals to full CMOS levels [VIL < 0.4V and VOH > (VCC - 0.4V)]. Severe ground pin current disturbances can also occur due to the undershoot of fast digital input signals. Undershoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to LTC2404/LTC2408. For reference, on a regular FR-4 board, signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. The solution is to carefully terminate all transmission lines close to their characteristic impedance. Parallel termination near the LTC2404/LTC2408 input pins will eliminate this problem but will increase the driver 22 U W U U LTC2404/LTC2408 APPLICATIONS INFORMATION power dissipation. A series resistor between 27 and 56 placed near the driver or near the LTC2404/LTC2408 pin will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology. Driving the Input and Reference The analog input and reference of the typical delta-sigma analog-to-digital converter are applied to a switched capacitor network. This network consists of capacitors switching between the analog input (ADCIN), ground and the reference (VREF). The result is small current spikes seen at both ADCIN and VREF. A simplified input equivalent circuit is shown in Figure 12. The key to understanding the effects of this dynamic input current is based on a simple first order RC time constant model. Using the internal oscillator, the internal switched capacitor network of the LTC2404/LTC2408 is clocked at 153,600Hz corresponding to a 6.5s sampling period. Fourteen time constants are required each time a capacitor is switched in order to achieve 1ppm settling accuracy. Therefore, the equivalent time constant at VIN and VREF should be less than 6.5s/14 = 460ns in order to achieve 1ppm accuracy. Input Current (VIN) If complete settling occurs on the input, conversion results will be uneffected by the dynamic input current. If the settling is incomplete, it does not degrade the linearity ADCVCC (PIN 2) IREF VREF IREF MUXVCC (PIN 8) RSW 75 MUXOUT IIN(MUX) ADCVCC (PIN 2) IIN(LEAK) IIN(LEAK) RSW 5k fOUT = 50Hz, INTERNAL OSCILLATOR: f = 128kHz fOUT = 60Hz, INTERNAL OSCILLATOR: f = 153.6kHz EXTERNAL OSCILLATOR: 2.56kHz f 307.2kHz GND 24048 F12 SELECTED CHANNEL I IN(MUX) CHX Figure 12. LTC2404/LTC2408 Equivalent Analog Input Circuit U W U U performance of the device. It simply results in an offset/ full-scale shift, see Figure 13. To simplify the analysis of input dynamic current, two separate cases are assumed: large capacitance at VIN (CIN > 0.01F) and small capacitance at VIN (CIN < 0.01F). If the total capacitance at VIN (see Figure 14) is small (< 0.01F), relatively large external source resistances (up to 20k for 20pF parasitic capacitance) can be tolerated without any offset/full-scale error. Figures 15 and 16 show a family of offset and full-scale error curves for various TUE 0 VREF/2 VIN VREF 24048 F13 Figure 13. Offset/Full-Scale Shift RSOURCE INTPUT SIGNAL SOURCE CIN CPAR 20pF CH0 TO CH7 LTC2404/ LTC2408 24048 F14 Figure 14. An RC Network at CH0 to CH7 RSW 5k IDC ADCIN RSW 5k AVERAGE INPUT CURRENT: IDC = 0.25(VIN - 0.5 * VREF) * f * CEQ CEQ 10pF (TYP) 23 LTC2404/LTC2408 APPLICATIONS INFORMATION 50 40 OFFSET ERROR (ppm) OFFSET ERROR (ppm) VCC = 5V VREF = 5V VIN = 0V TA = 25C 30 20 CIN = 0pF CIN = 100pF CIN = 1000pF CIN = 0.01F 10 0 1 10 1k 100 RSOURCE () 10k 100k 24048 F15 Figure 15. Offset vs RSOURCE (Small C) 0 VCC = 5V VREF = 5V VIN = 5V TA = 25C FULL-SCALE ERROR (ppm) FULL-SCALE ERROR (ppm) -10 -20 -30 CIN = 0pF CIN = 100pF CIN = 1000pF CIN = 0.01F -40 -50 1 10 1k 100 RSOURCE () 10k 100k 24048 F16 Figure 16. Full-Scale Error vs RSOURCE (Small C) small valued input capacitors (CIN < 0.01F) as a function of input source resistance. For large input capacitor values (CIN > 0.01F), the input spikes are averaged by the capacitor into a DC current. The gain shift becomes a linear function of input source resistance independent of input capacitance, see Figures 17 and 18. The equivalent input impedance is 1.66M. This results in 1.5A of input dynamic current at the extreme values of VIN (VIN = 0V and VIN = VREF, when VREF = 5V). This corresponds to a 0.3ppm shift in offset and full-scale readings for every 1 of input source resistance. While large capacitance applied to one of the multiplexer channel inputs may result in offset/full-scale shifts, large 24 U W U U 300 VCC = 5V VREF = 5V 250 VIN = 0V TA = 25C 200 CIN = 1F CIN = 10F CIN = 0.1F 150 100 CIN = 0.01F 50 0 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE () 24048 F17 Figure 17. Offset vs RSOURCE (Large C) 0 -50 -100 CIN = 0.1F -150 -200 -250 -300 0 200 400 600 RSOURCE () 800 1000 24048 F18 CIN = 0.01F VCC = 5V VREF = 5V VIN = 5V TA = 25C CIN = 1F CIN = 10F Figure 18. Full-Scale Error vs RSOURCE (Large C) capacitance applied to the MUXOUT/ADCIN results in linearity errors. The 75 on-resistance of the multiplexer switch is nonlinear with input voltage. If the capacitance at node MUXOUT/ADCIN is less than 0.01F, the linearity is not degraded. On the other hand, excessive capacitance (> 0.01F) results in incomplete settling as a function of the multiplexer on-resistance. Hence, the nonlinearity of the multiplexer switch is seen in the overall transfer characteristic. In addition to the input current spikes, the input ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (10nA max), results in a fixed offset shift of 10V for a 10k source resistance. LTC2404/LTC2408 APPLICATIONS INFORMATION Reference Current (VREF) Similar to the analog input, the reference input has a dynamic input current. This current has negligible effect on the offset. However, the reference current at VIN = VREF is similar to the input current at full-scale. For large values of reference capacitance (CVREF > 0.01F), the full-scale error shift is 0.3ppm/ of external reference resistance independent of the capacitance at VREF, see Figure 19. If the capacitance tied to VREF is small (CVREF < 0.01F), an input resistance of up to 20k (20pF parasitic capacitance at VREF) may be tolerated, see Figure 20. Unlike the analog input, the integral nonlinearity of the device can be degraded with excessive external RC time 600 500 FULL-SCALE ERROR (ppm) 400 300 200 CVREF = 0.1F 100 CVREF = 0.01F 0 0 200 400 600 800 RESISTANCE AT VREF () 1000 24048 F19 VCC = 5V VREF = 5V VIN = 5V TA = 25C INL ERROR (ppm) CVREF = 10F CVREF = 1F Figure 19. Full-Scale Error vs RVREF (Large C) 50 FULL-SCALE ERROR (ppm) INL ERROR (ppm) VCC = 5V VREF = 5V 40 V = 5V IN TA = 25C 30 CVREF = 100pF CVREF = 1000pF 20 CVREF = 0.01F 10 0 CVREF = 0pF -10 -20 1 10 100 10k 1k RESISTANCE AT VREF() 100k 24048 F20 Figure 20. Full-Scale Error vs RVREF (Small C) U W U U constants tied to the reference input. If the capacitance at node VREF is small (CVREF < 0.01F), the reference input can tolerate large external resistances without reduction in INL, see Figure 21. If the external capacitance is large (CVREF > 0.01F), the linearity will be degraded by 0.15ppm/ independent of capacitance at VREF, see Figure 22. In addition to the dynamic reference current, the VREF ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (10nA max), results in a fixed full-scale shift of 10V for a 10k source resistance. 50 40 30 20 VCC = 5V VREF = 5V TA = 25C CVREF = 0pF CVREF = 100pF CVREF = 1000pF CVREF = 0.01F 10 0 -10 1 10 100 1k 10k RESISTANCE AT VREF () 100k 24048 F21 Figure 21. INL Error vs RVREF (Small C) 160 140 120 100 80 60 40 20 0 -20 0 VCC = 5V VREF = 5V TA = 25C CVREF = 0.1F CVREF = 1F CVREF = 10F CVREF = 0.01F 800 200 600 400 RESISTANCE AT VREF () 1000 24048 F22 Figure 22. INL Error vs RVREF (Large C) 25 LTC2404/LTC2408 APPLICATIONS INFORMATION ANTIALIASING One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2404/LTC2408 significantly simplify antialiasing filter requirements. The digital filter provides very high rejection except at integer multiples of the modulator sampling frequency (fS), see Figure 23. The modulator sampling frequency is 256 * FO, where FO is the notch frequency (typically 50Hz or 60Hz). The bandwidth of signals not rejected by the digital filter is narrow ( 0.2%) compared to the bandwidth of the frequencies rejected. As a result of the oversampling ratio (256) and the digital filter, minimal (if any) antialias filtering is required in front of the LTC2404/LTC2408. If passive RC components are placed in front of the LTC2404/LTC2408, the input dynamic current should be considered (see Input Current section). In cases where large effective RC time constants are used, an external buffer amplifier may be required to minimize the effects of input dynamic current. The modulator contained within the LTC2404/LTC2408 can handle large-signal level perturbations without saturating. Signal levels up to 40% of VREF do not saturate the analog modulator. These signals are limited by the input ESD protection to 300mV below ground and 300mV above VCC. The LTC2408's Resolution and Accuracy Allows You to Measure Points in a Ladder of Sensors In many industrial processes, for example, cracking towers in petroleum refineries, a group of temperature measurements must be related to one another. A series of platinum RTDs that sense slow changing temperatures can be configured into a resistive ladder, using the LTC2408 to sense each node. This approach allows a single excitation current passed through the entire ladder, reducing total supply current consumption. In addition, this approach requires only one high precision resistor, thereby reducing cost. A group of up to seven temperatures can be measured as a group by a single LTC2408 in a loop-powered remote acquisition unit. In the example shown in Figure 24, the excitation current is 240A at 0C. The LTC2408 requires 300A, leaving nearly 3.5mA for the remainder of the remote transmitter. The resistance of any of the RTDs (PT1 to PT7) is determined from the voltage across it, as compared to the voltage drop across the reference resistor (R1). This is a ratiometric implementation where the voltage drop across R1 is given by VREF - VCH1. Channel 7 is used to measure the voltage on a representative length of wire. If the same type and length of wire is used for all connections, then errors associated with the voltage drops across all wiring can be removed in software. The contribution of wiring drop can be scaled if wire lengths are not equal. Gain can be added to this circuit as the total voltage drop across all the RTDs is small compared to ADC full-scale range. The maximum recommended gain is 40, as limited by both amplifier noise contribution, as well as the maximum voltage developed at CH0 when all sensors are at the maximum temperature specified for platinum RTDs. Adding gain requires that one of the resistors (PT1 to PT7) be a precision resistor in order to eliminate the error associated with the gain setting resistors R2 and R3. Note, that if a precision (100 to 400) resistor is used in place of one of the RTDs (PT7 recommended), R1 does not need to be a high precision resistor. Although the substitution of a precision reference resistor for an RTD to determine gain may suggest that R2 and R3 (and R1) need not be precise, temperature fluctuations due to airflow may appear as noise that cannot be removed in firmware. Conse- 0 -20 -40 REJECTION (dB) -60 -80 -100 -120 -140 0 fS/2 INPUT FREQUENCY 24048 F23 fS Figure 23. Sinc4 Filter Rejection 26 U W U U LTC2404/LTC2408 APPLICATIONS INFORMATION 5V 300A R2 6 47F LTC1634-2.5 3 4 R1 20.1k 0.1% 5 2 5V OPTIONAL GAIN BLOCK 6 + UP TO SEVERAL HUNDRED FEET. ALL SAME WIRE TYPE PT1 100 PLATINUM RTD OPTIONAL PROTECTION RESISTORS 5k MAX PT2 TO PT3-PT6 PT7 Figure 24. Measuring Up to Seven RTD Temperatures with One Reference Resistor and One Reference Current quently, these resistors should be low temperature coefficient devices. The use of higher resistance RTDs is not recommended in this topology, although the inclusion of one 1000 RTD at the top on the ladder will have minimal impact on the lower elements. The same caveat applies to fast changing temperatures. Any fast changing sensors should be at the top of the ladder. The LTC2408's Uncommitted Multiplexer Finds Use in a Programmable Gain Scheme If the multiplexer in the LTC2408 is not committed to channel selection, it can be used to select various signalprocessing options such as different gains, filters or attenuator characteristics. In Figure 25, the multiplexer is shown selecting different taps on an R/2R ladder in the feedback loop of an amplifier. This example allows selection of gain from 1 to 128 in binary steps. Other feedback networks could be used to provide gains tailored for specific purposes. (For example, 1x, 1.1x, 1.41x, 2x, 2.028x, 5x, 10x, 40x, etc.) Alternatively, different bandpass U W U U 0.1F + - 7 LTC1050 4 R3 R2 5V 7 MUXOUT 9 CH0 10 CH1 11 CH2 12 CH3 13 CH4 14 CH5 15 CH6 17 CH7 LTC2408 GND 1, 5, 6, 16, 18, 22, 27, 28 FO 2404/08 F24 4 ADCIN 3 2, 8 VREF VCC CSADC CSMUX SCK CLK DIN SDO 23 20 25 19 21 24 1F 8-CHANNEL MUX 24-BIT ADC VCC 26 characteristics or signal inversion/noninversion could be selected. The R/2R ladder can be purchased as a network to ensure tight temperature tracking. Alternatively, resistors in a ladder or as separate dividers can be assembled from discrete resistors. In the configuration shown, the channel resistance of the multiplexer does not contribute much to the error budget, as only input op amp current flows through the switch. The LTC1050 was chosen for its low input current and offset voltage, as well as its ability to drive the input of a ADC. Insert Gain or Buffering After the Multiplexer Separate MUXOUT and ADCIN terminals permit insertion of a gain stage between the MUX and the ADC. If passive filtering is used at the input to the ADC, a buffer amplifier is strongly recommended to avoid errors resulting from the dynamic ADC input current. If antialiasing is required, it should be placed at the input to the MUX. If bandwidth limiting is required to improve noise performance, a filter with a -3dB point at 1500Hz will reduce the effective total 27 LTC2404/LTC2408 APPLICATIONS INFORMATION 5V VIN 3 + LTC1050 2 - 5V 0.1V TO VCC 7 MUXOUT 4 ADCIN 3 2, 8 VREF VCC CSADC CSMUX 8-CHANNEL MUX 24-BIT ADC SCK CLK DIN SDO LTC2408 GND 1, 5, 6, 16, 18, 22, 27, 28 FO 2404/08 F25 10k 20k 20k 20k 20k 20k 20k 20k 10k 2 9 4 10 11 8 16 12 13 14 15 32 64 17 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 10k 10k 10k 10k 10k 10k 128 Figure 25. Using the Multiplexer to Produce Programmable Gains of 1 to 128 5V OPTIONAL BANDWIDTH LIMIT C1 0.022F R1 5.1k 9 CH0 10 CH1 11 CH2 12 CH3 ANALOG INPUTS 13 CH4 14 CH5 15 CH6 17 CH7 LTC2408 GND 1, 5, 6, 16, 18, 22, 27, 28 FO 2404/08 F26 Figure 26. Inserting Gain Between the Multiplexer and the ADC Input 28 U 3 2 W U U AV = 1, 2, 4...128 6 1F 23 20 25 19 21 24 VCC 26 + - 7 6 R4 5K MAY BE REQUIRED BY OTHER AMPLIFIERS (IS REQUIRED BY BIPOLAR AMPLIFIERS) LTC1050 4 R3 200k R2 5.1K C2 OPTIONAL GAIN AND ROLL-OFF 7 MUXOUT 4 ADCIN 3 2, 8 VREF VCC CSADC CSMUX 8-CHANNEL MUX 24-BIT ADC SCK CLK DIN SDO 23 20 25 19 21 24 VCC 5V 10F 26 LTC2404/LTC2408 APPLICATIONS INFORMATION noise bandwidth of the system to 6Hz. The noise bandwidth of the LTC2408 without any input bandwidth limiting is approximately 150Hz. A roll-off at 1500Hz eliminates all higher order images of the base bandwidth of 6Hz. In the example shown, the optional bandwidthlimiting filter has a - 3dB point at 1450Hz. This filter can be inserted after the multiplexer provided that higher source impedance prior to the multiplexer does not reduce the - 3dB frequency, extending settling time, and resulting in charge sharing between samples. The settling time of this filter to 20+ bits of accuracy is less than 2ms. In the presence of external wideband noise, this filter reduces the apparent noise by a factor of 5. Note that the noise bandwidth for noise developed in the amplifier is 150Hz. In the example shown, the gain of the amplifier is set to 40, the point at which amplifier noise gain dominates the LTC2408 noise. Input voltage range as shown is then 0V to 125mV DC. The recommended capacitor at C2 for a gain of 40 would be 560pF. Interfacing the LTC2404/LTC2408 to the 68HC11 Microcontroller The listing in Figure 28 is a simple assembler routine for the 68HC11 microcontroller. It uses PORT D, configuring it for SPI data transfer between the controller and the LTC2408. The program shows how to select and enable a MUX channel and retrieve conversion data. Figure 27 shows the simple 4-wire SPI connection. ********************************************************** * * * This example program loads multiplexer channels selection data into * * the LTC2408's internal MUX and then transfers the LTC2408's 32-bit * * output conversion result to four consecutive 8-bit memory locations. * * * ********************************************************** * *************************************** * 68HC11 register definitions * *************************************** * PORTD EQU $1008 Port D data register * " - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD " DDRD EQU $1009 Port D data direction register SPCR EQU $1028 SPI control register * "SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0" SPSR EQU $1029 SPI status register * "SPIF,WCOL, - ,MODF; - , - , - , - " SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter * * RAM variables to hold the LTC2408's 32 conversion result * LTC2408 U W U U The code begins by declaring variables and allocating four memory locations to store the 32-bit conversion result and a fifth location to store the MUX channel address. This is followed by initializing PORT D's SPI configuration. The program then enters the main sequence. It begins by sending the MUX channel data. It then activates the LTC2408's serial interface by setting the SS output low, sending a logic low to CSADC/CSMUX. This also activates the selected MUX channel. It next waits in a loop for a logic low on the data line, signifying end-of-conversion. After the loop is satisfied, four SPI transfers are completed, retrieving the conversion. The main sequence ends by setting SS high. This places the LTC2408's serial interface in a high impedance state and initiates another conversion. The program in Figure 30 modifies the MUX channel selection routine in Figure 28's listing for selection of 16 channels. Figure 29 shows the connections between the LTC1391, LTC2408 and the 68HC11 controller. CLK SCK SD0 CSADC CSMUX DIN 19 25 24 23 20 21 68HC11 SCK (PD4) MISO (PD2) SS (PD5) MOSI (PD3) 24048 F27 Figure 27. Connecting the LTC2408 to a 68HC11 MCU Using the SPI Serial Interface 29 LTC2404/LTC2408 APPLICATIONS INFORMATION DIN1 EQU $00 This memory location holds the LTC2408's bits 31 - 24 DIN2 EQU $01 This memory location holds the LTC2408's bits 23 - 16 DIN3 EQU $02 This memory location holds the LTC2408's bits 15 - 08 DIN4 EQU $03 This memory location holds the LTC2408's bits 07 - 00 MUX EQU $04 This memory location holds the MUX address data * *************************************** * Start GETDATA Routine * *************************************** * ORG $C000 Program start location * LDS $CFFF Top of C page RAM, beginning location of stack INIT1 LDAA #$2F -,-,1,0;1,1,1,1 * -, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X STAA PORTD Keeps SS* a logic high when DDRD, bit 5 is set LDAA #$38 -,-,1,1;1,0,0,0 STAA DDRD SS* , SCK, MOSI are configured as Outputs * MISO, TxD, RxD are configured as Inputs * DDRD's bit 5 is a 1 so that port D's SS* pin is a general output LDAA #$50 STAA SPCR The SPI is configured as Master, CPHA = 0, CPOL = 0 * and the clock rate is E/2 * (This assumes an E-Clock frequency of 4MHz. For higher * E-Clock frequencies, change the above value of $50 to a * value that ensures the SCK frequency is 2MHz or less.) GETDATA PSHX PSHY PSHA LDX #$0 The X register is used as a pointer to the memory * locations that hold the conversion data LDY #$1000 * ******************************* * The next routine sends data to the * * LTC2408 an sets its MUX channel * ******************************* * LDAA $MUX Retrieve MUX address ORAA #$08 Set the MUX's ENABLE bit STAA SPDR Transfer Accum. A contents to SPI register to initiate * serial transfer WAITMUX LDAA SPSR Get SPI transfer status BPL WAITMUX If the transfer is not finished, read status * *************************************** * Enable the LTC2408 * *************************************** * BCLR PORTD,Y %00100000 This sets the SS* output bit to a logic * low, selecting the LTC2408 * *************************************** * The next short loop waits for the * * LTC2408's conversion to finish before * * starting the SPI data transfer * *************************************** * CONVEND LDAA PORTD Retrieve the contents of port D ANDA #%00000100 Look at bit 2 * Bit 2 = Hi; the LTC2408's conversion is not * complete * Bit 2 = Lo; the LTC2408's conversion is complete BNE CONVEND Branch to the loop's beginning while bit 2 remains * high 30 U W U U LTC2404/LTC2408 APPLICATIONS INFORMATION * *************************************** * The SPI data transfer * *************************************** * TRFLP1 LDAA #$0 Load accumulator A with a null byte for SPI transfer STAA SPDR This writes the byte into the SPI data register and * starts the transfer WAIT1 LDAA SPSR This loop waits for the SPI to complete a serial * transfer/exchange by reading the SPI Status Register BPL WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR's * MSB and is set to one at the end of an SPI transfer. The * branch will occur while SPIF is a zero. LDAA SPDR Load accumulator A with the current byte of LTC2408 data * that was just received STAA 0,X Transfer the LTC2408's data to memory INX Increment the pointer CPX #DIN4+1 Has the last byte been transferred/exchanged? BNE TRFLP1 If the last byte has not been reached, then proceed to * the next byte for transfer/exchage BSET PORTD,Y %00100000 This sets the SS* output bit to a logic * high, de-selecting the LTC2408 PULA Restore the A register PULY Restore the Y register PULX Restore the X register RTS Figure 28. LTC2408-68HC11 MCU Digital Interface Routine 7 MUXOUT 9 TO 17 CH0 TO CH7 LTC1391 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 1 2 3 4 5 6 7 8 S0 S1 S2 S3 S4 S5 S6 S7 D 15 10 CLK 11 CS 13 DOUT 12 DIN LTC2408 1, 5, 6, 16, 18, 22, 27, 28 Figure 29. Combining the LTC2408 with the LTC1391 for 16 Input Channels U W U U 5V 4 ADCIN 3 2, 8 VREF VCC CSADC CSMUX 24-BIT ADC SCK CLK DIN SDO 23 20 25 19 21 24 VCC 10F 68HC11 SS (PD5) SCK (PD4) MOSI (PD3) MISO (PD2) GND FO 26 2404/08 F29 31 LTC2404/LTC2408 APPLICATIONS INFORMATION ***************************************************************************** * * * This example program loads multiplexer channels selection data into * * either the LTC2408's internal MUX or an external LTC1391 MUX. It then * * transfers the LTC2408's 32-bit output conversion result to four * * consecutive 8-bit memory locations. * * * ***************************************************************************** * *************************************** * 68HC11 register definitions * *************************************** * PORTD EQU $1008 Port D data register * " - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD " DDRD EQU $1009 Port D data direction register SPCR EQU $1028 SPI control register * "SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0" SPSR EQU $1029 SPI status register * "SPIF,WCOL, - ,MODF; - , - , - , - " SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter * * RAM variables to hold the LTC2408's 32 conversion result * DIN1 EQU $00 This memory location holds the LTC2408's bits 31 - 24 DIN2 EQU $01 This memory location holds the LTC2408's bits 23 - 16 DIN3 EQU $02 This memory location holds the LTC2408's bits 15 - 08 DIN4 EQU $03 This memory location holds the LTC2408's bits 07 - 00 MUX EQU $04 This memory location holds the MUX address data * *************************************** * Start GETDATA Routine * *************************************** * ORG $C000 Program start location INIT1 LDAA #$2F -,-,1,0;1,1,1,1 * -, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X STAA PORTD Keeps SS* a logic high when DDRD, bit 5 is set LDAA #$38 -,-,1,1;1,0,0,0 STAA DDRD SS* , SCK, MOSI are configured as Outputs * MISO, TxD, RxD are configured as Inputs * DDRD's bit 5 is a 1 so that port D's SS* pin is a general output LDAA #$50 STAA SPCR The SPI is configured as Master, CPHA = 0, CPOL = 0 * and the clock rate is E/2 * (This assumes an E-Clock frequency of 4MHz. For higher * E-Clock frequencies, change the above value of $50 to a * value that ensures the SCK frequency is 2MHz or less.) GETDATA PSHX PSHY PSHA LDX #$0 The X register is used as a pointer to the memory * locations that hold the conversion data LDY #$1000 * *************************************** * The next routine sends data to the * * LTC2408 an sets its MUX channel * *************************************** * LDAA MUX Retrieve MUX address TAB Save contents of Accum. A SUBA #$07 Is the MUX address in the low nibble BLE ENLWMX If it is, branch to enable the LTC2408's internal MUX TBA Restore contents of Accum. A ORAA #$80 Enable the LTC1391 external MUX BRA MUXSPI Go to SPI transfer2400 32 U W U U LTC2404/LTC2408 APPLICATIONS INFORMATION ENLWMX TBA ORAA MUXSPI STAA * WAITMUX LDAA #$08 SPDR SPSR BPL Restore contents of Accum. A Set the MUX's ENABLE bit Transfer Accum. A contents to SPI register to initiate serial transfer Get SPI transfer status WAITMUX If the transfer is not finished, read status * *************************************** * Enable the LTC2408 * *************************************** * BCLR PORTD,Y %00100000 This sets the SS* output bit to a logic * low, selecting the LTC2408 * *************************************** * The next short loop waits for the * * LTC2408's conversion to finish before * * starting the SPI data transfer * *************************************** * CONVEND LDAA PORTD Retrieve the contents of port D ANDA #%00000100 Look at bit 2 * Bit 2 = Hi; the LTC2408's conversion is not * complete * Bit 2 = Lo; the LTC2408's conversion is complete BNE CONVEND Branch to the loop's beginning while bit 2 remains * high * *************************************** * The SPI data transfer * *************************************** * TRFLP1 LDAA #$0 Load accumulator A with a null byte for SPI transfer STAA SPDR This writes the byte into the SPI data register and * starts the transfer WAIT1 LDAA SPSR This loop waits for the SPI to complete a serial * transfer/exchange by reading the SPI Status Register BPL WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR's * MSB and is set to one at the end of an SPI transfer. The * branch will occur while SPIF is a zero. LDAA SPDR Load accumulator A with the current byte of LTC2408 data * that was just received STAA 0,X Transfer the LTC2408's data to memory INX Increment the pointer CPX #DIN4+1 Has the last byte been transferred/exchanged? BNE TRFLP1 If the last byte has not been reached, then proceed to * the next byte for transfer/exchage BSET PORTD,Y %00100000 This sets the SS* output bit to a logic * high, de-selecting the LTC2408 PULA Restore the A register PULY Restore the Y register PULX Restore the X register RTS Figure 30. LTC2408/LTC1391-684C11 MCU Digital Interface Routine An 8-Channel DC-to-Daylight Digitizer The circuit in Figure 31 shows an example of the LTC2408's flexibility in digitizing a number of real-world physical phenomena--from DC voltages to ultraviolet light. All of the examples implement single-ended signal conditioning. Although differential signal conditioning is a preferred approach in applications where the sensor is a bridge- U W U U type, is located some distance from the ADC or operates in a high ambient noise environment, the LTC2408's low power dissipation allows circuit operation in close proximity to the sensor. As a result, conditioning the sensor output can be greatly simplified through the use of singleended arrangements. In those applications where differential signal conditioning is required, chopper 33 LTC2404/LTC2408 APPLICATIONS INFORMATION amplifier-based or self-contained instrumentation amplifiers (also available from LTC) can be used with the LTC2408. With the resistor network connected to CH0, the LTC2408 is able to measure DC voltages from 1mV to 1kV in a single range without the need for autoranging. The 990k resistor should be a 1W resistor rated for high voltage operation. Alternatively, the 990k resistor can be replaced with a series connection of several lower cost, lower power metal film resistors. The circuit connected to CH1 shows an LT1793 FET input operational amplifier used as an electrometer for high impedance, low frequency applications such as measuring pH. The circuit has been configured for a gain of 21; thus, the input signal range is -15mV VIN 250mV. An amplifier circuit is necessary in these applications because high output impedance sensors cannot drive switched-capacitor ADCs directly. The LT1793 was chosen for its low input bias current (10pA, max) and low noise (8nV/Hz) performance. As shown, the use of a driven guard (and TeflonTM standoffs) is recommended in high impedance sensor applications; otherwise, PC board surface leakage current effects can degrade results. The circuit connected to CH2 illustrates a precision halfwave rectifier that uses the LTC2408's internal ADC as an integrator. This circuit can be used to measure 60Hz, 120Hz or from 400Hz to 1kHz with good results. The LTC2408's internal sinc4 filter effectively eliminates any frequency in this range. Above 1kHz, limited amplifier gain-bandwidth product and transient overshoot behavior can combine to degrade performance. The circuit's dynamic range is limited by operational amplifier input offset voltage and the system's overall noise floor. Using an LTC1050 chopper-stabilized operational amplifier with a VOS of 5V, the dynamic range of this application covers approximately 5 orders of magnitude. The circuit configuration is best implemented with a precision, 3-terminal, 2-resistor 10k network (for example, an IRC PFC-D network) for R6 and R7 to maintain gain and temperature stability. Alternatively, discrete resistors with 0.1% initial tolerance and 5ppm/C temperature coefficient would also be adequate for most applications. Two channels (CH3 and CH4) of the LTC2408 are used to accommodate a 3-wire 100, Pt RTD in a unique circuit that allows true RMS/RF signal power measurement from audio to gigahertz (GHz) frequencies. The unique feature of this circuit is that the signal power dissipated in the 50 termination in the form of heat is measured by the 100 RTD. Two readings are required to compensate for the RTD's lead-wire resistance. The reading on CH4 is multiplied by 2 and subtracted from the reading on CH3 to determine the exact value of the RTD. While the LTC2408 is capable of measuring signals over a range of six decades, the implementation (mechanical, electrical and thermal) of this technique ultimately determines the performance of the circuit. The thermal resistance of the assembly (the 50/RTD mass to its enclosure) will determine the sensitivity of the circuit. The dynamic range of the circuit will be determined by the maximum temperature the assembly is rated to withstand, approximately 850C. Details of the implementation are quite involved and are beyond the scope of this document. Please contact LTC directly for a more comprehensive treatment of this implementation. In the circuit connected to the LTC2408's CH5 input, a thermistor is configured in a half-bridge arrangement that could be used to measure the case temperature of the RTD-based thermal power measurement scheme described previously. In general, thermistors yield very good resolution over a limited temperature range. Measurement resolution of 0.001C is possible; however, thermistor self-heating effects, thermistor initial tolerance and circuit thermal construction can combine to limit achievable resolution. For the half-bridge arrangement shown, the LTC2408 can measure temperature changes over 5 orders of magnitude. Connected to the LTC2408's CH6 input, an infrared thermocouple (Omega Engineering OS36-1) can be used in limited range, noncontact temperature measurement applications or applications where high levels of infrared light must be measured. Given the LTC2408's 0.3ppmRMS noise performance, measurement resolution using infrared thermocouples is approximately 0.03C--equivalent to the resolution of a conventional Type J thermocouple. Teflon is a trademark of Dupont Company. 34 U W U U LTC2404/LTC2408 APPLICATIONS INFORMATION These infrared thermocouples are self-contained: 1) they do not require external cold junction compensation; 2) they cannot use conventional open thermocouple detection schemes; and 3) their output impedances are high, approximately 3k. Alternatively, conventional thermocouples can be connected directly to the LTC2408 (not shown) and cold junction compensation can be provided by an external temperature sensor connected to a different channel (see the thermistor circuit on CH5) or by using the LT1025, a monolithic cold-junction compensator IC. The components connected to CH7 are used to sense daylight or photodiode current with a resolution of 300pA. In the figure, the photodiode is biased in photoconductive mode; however, the LTC2408 can accommodate either photovoltaic or photoconductive configurations. The photodiode chosen (Hammatsu S1336-5BK) produces an output of 500mA per watt of optical illumination. The output of the photodiode is dependent on two factors: active detector area (2.4mm * 2.4mm) and illumination intensity. With the 5k resistor, optical intensities up to 368W/m2 at 960nM (direct sunlight is approximately 1000W/m2) can be measured by the LTC2408. With a resolution of 300pA, the optical dynamic range covers 6 orders of magnitude. The application circuits shown connected to the LTC2408 demonstrate the mix-and-match capabilities of this multiplexed-input, high resolution ADC. Very low level signals and high level signals can be accommodated with a minimum of additional circuitry. PACKAGE DESCRIPTIO Dimensions in millimeters (inches) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 10.07 - 10.33* (0.397 - 0.407) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 5.20 - 5.38** (0.205 - 0.212) 0 - 8 0.13 - 0.22 (0.005 - 0.009) 0.55 - 0.95 (0.022 - 0.037) NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U U W U U 7.65 - 7.90 (0.301 - 0.311) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1.73 - 1.99 (0.068 - 0.078) 0.65 (0.0256) BSC 0.25 - 0.38 (0.010 - 0.015) 0.05 - 0.21 (0.002 - 0.008) G28 SSOP 1098 35 LTC2404/LTC2408 TYPICAL APPLICATION GUARD RING ELECTROMETER INPUT (pH, PIEZO) 3 5V + R4 1k 60Hz AC INPUT R6 10k, 0.1% 3-WIRE R-PACK R7 10k, 0.1% 5V 2 RT 3 7 R9 1k 1% R10 5k 1% 7 MUXOUT 9 CH0 10 CH1 R8 100, 5% 20mV TO 80mV R11 24.9k, 0.1% V REF 5V 11 CH2 12 CH3 13 CH4 14 CH5 15 CH6 17 CH7 LTC2408 GND 1, 5, 6, 16, 18, 22, 27, 28 8-CHANNEL MUX 24-BIT ADC 4 ADCIN 1F - LTC1050 IN914 6 + 4 -5V 60Hz-RF RF POWER 50 100 Pt RTD (3-WIRE) J1 <1mV FORCE SENSE 2.7V AT 0C 0.9V AT 40C R12 24.9k, 0.1% V REF 5V LOCAL TEMP THERMISTOR 10k NTC OMEGA 0S36-01 INFRARED INFRARED THERMOCOUPLE R13 5k 0.1% 5V DAYLIGHT HAMAMATSU PHOTODIODE S1336-5BK -2.2mV to 16mV 0V to 4V J2 J3 50 LOAD BONDED TO RTD ON INSULATED MOUNTING RELATED PARTS PART NUMBER LTC1050 LT1236 LT1793 LTC2400 LTC2424/LTC2428 DESCRIPTION Precision Chopper Stabilized Op Amp Precision Bandgap Reference Low Noise JFET Input Op Amp 24-Bit Micropower ADC in SO-8 20-Bit 4-/8-Channel ADCs COMMENTS No External Components, 5V Offset, 1.6VP-P 0.05% Max Initial Accuracy, 5ppm/C Drift 10pA Max Input Bias Current, Low Voltage Noise: 8nV <4ppm INL, No Missing Codes, 4ppm Full Scale 1.2ppm Noise, 8ppm INL, Fast Mode 24048fa LT/LCG 0700 2K REV A * PRINTED IN USA 36 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U + - 7 6 R5 5k, 1% DC VOLTMETER INPUT 1mV TO 1000V R1 900k 0.1%, 1W, 1000 WVDC R2 4.7k 0.1% 0V TO 5V LT1793 2 4 -5V R3, 10k -60mV TO 4V LT1236CS8-5 6 2 OUT IN GND 4 C1, 0.1F 5V MAX 5V REF 10F + + 8V 100F 5V 3 2, 8 VREF VCC 23 20 19, 25 21 24 MPU + 1F SERIAL DATA LINK MICROWIRE AND SPI COMPATABLE IN914 CSADC CSMUX CLK DIN SDO FO 24048 F31 26 INTERNAL OSC SELECTED FOR 60Hz REJECTION Fiugre 31. Measure DC to Daylight Using the LTC2408 (c) LINEAR TECHNOLOGY CORPORATION 1999 |
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